The Stack Machine Computer
Project
MTM Scientific, Inc
The
Stack Machine Computer Project was started after reading a book by Per
Brinch Hansen: "Programming a Personal Computer". I was also intriqued
by writings of Nikolaus Wirth about the Pascal programming language.
The unique properties and simplicity of stack machine computers started
my search for a suitable hardware platform for experimentation. I found
a good summary of historical stack machines in a book by
Philip Koopman: "Stack Computers, The New Wave", however obtaining
off-the-shelf stack machine hardware was found to be quite challenging.
Several historical papers on the architecture, operation and hardware
design of simple computers encouraged my consideration of building a
stack machine computer from discrete components. Notably a paper by
Bradford Rodriquez: "A Minimal TTL Processor for Architecture
Exploration", and a paper by Richard Eckert: "Micro-Programmed Versus
Hardwared Control Units: How Computers Really Work". Of these two
papers, I found the Eckert description of simple a computer
architecture
to be especially amenable to construction and modification for my
purposes to create a stack machine.
Common to both simple computer descriptions was the use of an
off-the-shelf Arithmetic Logic Unit (ALU), the 74LS181. Although
obsolete, this particular IC has the wonderful ability to perform
useful mathematical and logical operations while being controlled using
TTL logic. The 74LS181 ALU is easily sourced on the secondary IC
markets,
such as EBAY.
Figure 1. Eckert
Computer Architecture
In Figure 1, The components shown are as follows: PC is the Program
Counter, MAR is the Memory Address Register, RAM is Random Access
Memory (which can be RAM and ROM), MDR is the Memory Data Register, ACC
is the ALU Accumulator, ALU is the Arithmetic Logic Unit, B is the 2nd
ALU Register, IR is the Instruction Register and CONTROL is the
Hardware Control Matrix. We have annotated the original diagram with
additional information for clarity, as shown in Figure 2.
Figure 2. Annotated
Eckert
Computer Architecture
In the basic implementation of the computer architecture described by
Eckert, there is a 12 bit bus consisting of 8 data bits and 4 opcode
bits. The computer has 8 instructions and a cyclic ring counter to
provide 6 sequential trigger pulses. There are a total of 16 controls
signals for controlling the individual IC's. I combined these
functions with the CLK (Clock), RST (Reset), GND (Ground) and +5V lines
to create a 50 channel breadboard bus. This arrangement provided 4
unassigned channels for future development purposes.
Figure 3. Eckert
Computer Backplane PCB
The breadboard backplane to implement the Eckert Computer is shown in
Figure 3. The design stategy was to make a basic backplane into which
individual breadboarding cards could be inserted, tested and modified
during the development phase. Since this platform is intended for
development, the backplane includes LED logic level indication of all
50 channels of the bus. Also included is a manual toggle switch for
single-stepping the bus clock.
Individual functional components of the computer architecture reside on
individual cards. A partially assembled computer is shown in Figure 4.
A card was created especially for the purpose of doing prototype
circuit development. Also shown in Figure 3 is a view of the Ring
Counter card.
Figure 4. Computer
Backplane with Cards
The ALU card is shown in Figure 5. We have
annotated the functions of the individual ICs for clarity. The ALU
chips are combinatorial logic... they are NOT clocked. Therefore,
special care and thought are required for the A and B register timings.
The 74181 ALU chips are available in 2 different package sizes, 0.300"
and 0.600" width. Note that we have used the narrow packages to keep
the PCB layout more compact. We found it convenient to add functional
operative points on the ALU card for loading and enabling the A
register. We also added LED indicators for the 4 least significant bits
of the A register.
Figure 5. The ALU card
The memory card was especially challenging to design because the MDR
(Memory Data Register) must transfer data in both directions. This
function is available in the 74F543 Octal Registered Transceiver. We
forgot to tie the unused address lines on the SRAM to a stable logic
state, which is why the resistors are present in the photo of Figure 6.
(This condition exhibits as intermittent faults and was very difficult
to troubleshoot!) Because of possible race conditions between the
registers and SRAM we used a TTL delay line for some of the enable
signals. The LEDs were added as an easily visible indicator of bus
conditions on the board. We added some capacitance to the power
supply line as a precaution, but during the early phases of development
the clock speed has been very slow... only a few hertz. Note that the
Memory Card was designed to also accept ROM programmable memory in the
wide DIP packages, and eventually we will install ZIF sockets for easy
switching.
Figure 6. The Memory card
We found it was challenging to do the initial checkout of individual
board functions because of the tendency of TTL inputs to drift up to a
weak logic 'high' level. Therefore we created a special board for the
bus which tie all lines to a logic level 'low' using an array of
resistors. We found that generally a 1K resistor was sufficient
to pull lines to Logic "0". However, in the case of the ALU we found
the S0, S1, S2, S3 function control lines had a high internal fanout
and nearly 100 ohms of resistance was required. This was also a
difficult problem to find troubleshooting, and ran contrary to
expectations for a packaged TTL IC.
Figure 7. Bus
Termination Card
Figure 8. Complete Prototype Eckert Computer
The original paper by Eckert is quite specific
about the sequence of digital signals sent to control various
operations, such as enabling signals on the bus and loading signals
from the bus. We found that enabling and loading signals to the bus at
the same time created undesirable race conditions. To avoid race
conditions we implemented a short 50 ns delay in the loading operations
by using EP9206-50 delay ICs. We took this approach to preserve the
original design as closely as possible.
The boards were designed using the free design software from Express
PCB. We have used this software for PCB design for about 15 years
and have been very happy with it. There is also a companion program
available for creating circuit schematics. Most of the IC components
have been purchased on the secondary market, such as EBAY.
We found installing indicator LEDs for many of the digital signal lines
was invaluable. We also made a habit of labeling vias with the name of
the signal, which made for very convenient test points using a
multimeter probe. Placing the separate computer functions on individual
cards was especially helpful for testing. This approach also allows
individual cards to be revised and improved without affecting the other
cards. We intend to implement a stack using the same approach.
Update: Here is a photo of the cards comprising the computer as of
September, 2020.
Resource List:
The paper by Eckert which forms the basis for this project. I am using
the hardwired version of the controller.
http://www.cs.binghamton.edu/~reckert/hardwire3new.html
The paper by Rodriguez that describes using the 74181 ALU in a homebrew
'PISC' computer.
https://bradrodriguez.com/papers/piscedu2.htm
The book by Koopman about Stack Computers, available online.
http://users.ece.cmu.edu/~koopman/stack_computers/index.html
A webpage by Sukuba with an excellent description of a 4-bit homebrew
CPU.
http://jaromir.xf.cz/fourbit/fourbit.html
A book by Joseph D. Greenfield which describes
construction and operation of a small computer very similar to the
design discussed here: "Practical Digital Design Using ICs", 2nd
edition, 1983. See especially Chapter 16. This is a great book!
